/*
		This defines all the memory mapped registers the IO adapter itself provides
*/

// for use with  USHORT * 
#define	PCIO_INT_SEL	0x100	// PC I/O (write) interrupt select latch 
#define	PCIO_CONFIG		0x100	// PC I/O (read) configuration latch 
#define	PCIO_INT_READ	0x101	// PC I/O (read) interrupt latch -- Read once only
#define PCIO_STRB_CTRL  0x101	// Analog/Digital strobe control -- write only !!
#define	TMR_BASE_LSW	0x104	// Low  word for tmr1
#define	TMR_BASE_MSW	0x107	// upper word for tmr1
#define TMR_BASE_CTRL   0x10a	// RESET, RUN
#define PCIO_RESET		0x111   // reset the THC and everything on the pci io card


// Index defines for timer LSW, MSW and CTRL_BASE
#define TMR1			0
#define TMR2			1
#define TMR3			2
#define TMR1_CTRL      (TMR_BASE_CTRL + TMR1)   
#define TMR2_CTRL      (TMR_BASE_CTRL + TMR2) 
#define TMR3_CTRL      (TMR_BASE_CTRL + TMR3)


// these two go along with TMRn_CTRL
#define TMR_CTRL_RESET  0x1    // Resets Counter (stops counting, removes interrupt
#define TMR_CTRL_RUN    0x2    // Starts counter 


// for reg PCIO_INT_SEL
#define ADAPTER_INT_EN	0x00	// enables only adapter internal interrupts
#define ALL_INT_EN		0x80	// enables cabel interrupt  and the adapter internal sources (timers & 2us) 
#define ALL_INT_DIS		0x10    /* Disables all interrupt sources and forces IRQ low */
#define DS_HS_ENABL		0x08	// This interrupt source is not used in the AOI implementaion
#define DIAG_ADDR_TST   0x20	// for diag purposes only -- Not used in AOI
#define DIAG_CH_BSY_TST 0x40	// for diag purposes only -- Not used in AOI

// FOR PCIO_INT_READ
#define INT_TMR_BITS 0x7	// The timers are not used in the AOI, but an interrupt can be created anyway by
#define INT_Tmr1	0x1		// setting a timer and let it run. The driver's ISR hanles this interrupt locally
#define INT_Tmr2	0x2		// by clearing the timer register that caused the interrupt. Such an interrupt is 
#define INT_Tmr3	0x4		// not reflected to the application.
#define INT_2us		0x08	// This is generated by the IO adapter when a transfer on the cable fails to handshake after 2us 
#define INT_Dig		0x10	// This is where the WC140 controller issues an interrupt on
#define INT_Ana		0x20	// nothing is connected to this interrupt source in the AOI 
#define INT_Ext		0x40	// nothing is connected to this interrupt source in the AOI 

/* PCIO_RESET output port data definitions */
#define RST_IO		0x1	/* bit #0 = 1 resets the I/O board only */
#define RST_CABL	0x2	/* bit #1 = 1 sends a reset on the cable to the controller as well */
#define RST_ALL		0xff
#define RST_NONE	0x00


// defines for PCIO_STRB_CTRL 
#define A_STRB		0x40
#define D_STRB		0x00	
#define STROBE_A_RFLECT_BIT 0x40		// A_STRB bit reflects its setting on this bit in the PCIO_CONFIG register
